Dynamic random access memory (DRAM) is relatively inexpensive because each memory cell requires just an access transistor and a capacitor. In contrast, static random access memory (SRAM) requires at least six transistors per memory cell and is thus more expensive. DRAM is therefore the memory of choice for bulk storage in many electronic devices such as smartphones. Although DRAM is considerably less expensive, the relatively small capacitor used for each memory cell leaks charge over time such that it is necessary to refresh its contents periodically. In a refresh cycle for a DRAM, the contents of a memory cell are read out so that the memory cell's capacitor may be recharged appropriately. It is critical for a DRAM to refresh regularly according to its refresh schedule or it may lose its memory contents.
The enforcement of refresh operations according to the required refresh interval may be performed by a memory controller, which acts as the interface between a host processor and the corresponding DRAM. In conventional desktop and related applications, the memory controller is typically contained in a separate integrated circuit that is associated with the memory slots that accept the DRAM integrated circuits. Such a standalone memory controller may remain powered during normal operation independently of the host processor. But in modern mobile device applications such as smartphones, the memory controller is integrated with the host processor into a system-on-a-chip (SoC). Reducing power consumption by an SoC is a major goal in smartphone design as consumers do not want to constantly recharge their devices. It is thus conventional for a mobile device SoC to implement a sleep mode in which the memory controller is powered down either completely or partially. But the associated DRAM integrated circuit for the SoC must remain powered on during the sleep mode so that it may retain its memory contents. The refresh scheduling for a DRAM in mobile and related devices is thus controlled by the memory controller during an active mode of operation and by the DRAM itself during an idle or sleep mode of operation. To distinguish between the two types of refresh scheduling management, the memory-controller-managed refresh scheduling may be denoted as a “refresh mode” of operation whereas the DRAM-controlled refresh scheduling may be denoted as a “self-refresh mode” of operation.
Although this split control of the refresh scheduling in mobile devices allows the SoC to save power by entering the sleep mode, it is associated with unnecessary triggering of refresh cycles. For example, during the refresh mode of operation, the DRAM does not keep track of the refresh schedule timing since that is being managed by the memory controller. Upon resumption of the self-refresh mode of operation, the DRAM thus triggers a refresh operation. But the memory controller may have just triggered a refresh operation prior to the handoff to the self-refresh mode of operation such that the automatic triggering of a refresh operation by the DRAM upon the transition to the self-refresh mode was unnecessary. Similarly, the memory controller triggers a refresh operation at the resumption of a refresh mode of operation and termination of a self-refresh mode. Depending upon the timing of the last refresh cycle in the DRAM, the automatic triggering of a refresh operation by the memory controller upon the transition to the refresh mode may also be unnecessary. These unnecessary refresh cycles needlessly consume power. In addition, they increase memory latency since the DRAM is unavailable for read and write access until a refresh cycle is completed. This problem of increased latency and power consumption is aggravated in modern SoCs, which are engineered to enter sleep mode more frequently to minimize power consumption.
Accordingly, there is a need in the art for improved refresh scheduling in systems in which both the memory controller and the memory itself may control refresh scheduling.